1. Field of the Invention
The present invention relates in general to Global Positioning System (GPS) receivers, and in particular to a GPS Radio Frequency (RF) front end Integrated Circuit (IC) with a high level of monolithic integration.
2. Description of the Related Art
GPS receivers, once used primarily for military and surveying applications, are finding new uses in the commercial arena. Location services, emergency location using 911 (E911) phone calls for cellular telephones, personal GPS receivers, etc. are all part of current and emerging products and services enabled by using GPS receivers.
A typical GPS receiver uses an RF-IF/Converter section that selects, amplifies, filters, and downconverts the received GPS signals, and a baseband processing section to despread and detect the downconverted signals and determine a position of the GPS receiver. The RF section of today's GPS receivers are designed by each company that makes the receiver, and therefore, there are no established standards for such designs.
The analog RF designs typically comprise a Low Noise Amplifier (LNA) section with a two pole bandpass or preselect filter on the input, output, or both, followed by a single, double, or triple conversion receiver topology. The output of the last Intermediate Frequency (IF) section can be an amplitude limited Phase Modulated (PM) signal, which is typically called a 1 bit signal, or it can be a 2 bit system, typically consisting of a magnitude signal and sign signal. The analog RF section can also be partitioned at the output of a ≧2 bit A/D converter. The last IF stage may contain a limiter for a 1-bit system, or Automatic Gain Control (AGC) may be used to allow limiting to be performed by the ≧2 bit A/D converter.
For a single conversion receiver, the IF filtering usually follows an image reject mixer, and is typically a ≧2 pole design. The IF filter can be a balanced design to achieve common mode noise a rejection, or be a single ended filter. The typical image rejection performance of the image reject type mixer is approximately 20 dB or better, which is adequate for GPS.
A double conversion receiver typically comprises an LNA, an image rejection filter, a mixer, a first IF image rejection filter, a second mixer, and the final IF filter, and amplifier.
The gain of these systems is usually selected to be as small as feasible, while still allowing the final IF amplifier to achieve the desired output level, allowing for component variation. The gain of this system is typically governed by the noise bandwidth of the entire receive chain, that is the gain of the system is as needed to take in the noise power at the input, filter it, and then drive the receiver output to the proper levels.
The oscillator and/or frequency synthesizer sections of these receivers generate the desired timing, sampling, and mixer LO frequencies needed to downconvert the input RF signal to the proper IF frequencies. The necessary frequencies generated vary from design to design, and are generally unique to each receiver. Historically there has been little consistency among designs of GPS receivers. One common trait is that the input reference frequency must be very stable in terms of short term noise, or else the GPS signal processing will experience deleterious cycle slips in the signal tracking loops, resulting in loss of lock or other forms of impaired receiver performance.
A highly integrated RFIC that is compatible with the frequency plan disclosed in U.S. Pat. No. 5,897,605, which is incorporated by reference herein, provides utility in the implementation of GPS receivers.
Because there is little consistency between GPS receiver designs, it is difficult to design an RF portion of the GPS receiver that is compatible with more than one baseband processing section of a GPS receiver. Further, difference in frequency plans for GPS receivers make the RF portion and the baseband processing sections of different GPS receivers incompatible.
It can be seen, then, that there is a need in the art for a GPS receiver that can accept the RF GPS signal and convert it to a form that can be applied to a digital processing section, typically implemented as a GPS Processor ASIC. It can also be seen that there is a need in the art for a GPS RF front end that can be implemented primarily in a monolithic RFIC requiring a minimum of external components. It can also be seen that there is a need in the art for a GPS RF front end that uses receiver topologies that can be implemented using standard building blocks.